The present invention relates generally to an address buffer circuit used in a high-speed MOS (Metal Oxide Semiconductor) dynamic RAM (Random Access Memory) device.
In general, address signals of a TTL (Transistor Transistor Logic) level are supplied by an external circuit to a MOS dynamic RAM device. In this case, the low and high potentials of a TTL level are, for example, 0.8 volts and 2.0 through 2.4 volts, respectively. On the other hand, within the MOS dynamic RAM device, address signals of a MOS level whose low and high potentials are, for example, 0 volts and 5 volts, respectively, are used for accessing one memory cell among a memory cell matrix. Therefore, it is necessary to convert address signals of a TTL level into address signals of a MOS level. For carrying out such conversion, the device incorporates address buffer circuits therein.
One conventional address buffer circuit for converting an address signal of a TTL level into an address signal of a MOS level and its inverted signal comprises an input circuit for receiving the address signal of a TTL level, a pre-amplifier, a main amplifier and an output circuit for producing the address signal of a MOS level and its inverted signal. In order to operate this address buffer circuit, various kinds of clock signals are necessary.
However, in the above-mentioned conventional address buffer circuit, the circuit is of a relatively large scale. In addition, the operation speed is low, since the input circuit comprises a CR time-constant circuit. Further, the operation of the circuit is unstable, since a reference voltage which is dependent upon a power supply voltage is necessary and in addition, the main amplifier may be operated before the pre-amplifier comes into a predetermined state. Further, the malfunction of the output circuit may be invited by a dynamic operation.